1. Field of the Invention
The present invention relates to an integrated circuit and fabricating method thereof. More particularly, the present invention relates to a semiconductor device and method of fabricating the same.
2. Description of the Related Art
Typically, integrated circuit devices are interconnected via metal interconnects. The conventional method of fabricating metal interconnects includes forming a metal plug in a dielectric layer and then forming a metal line over a substrate to connect with the metal plug. FIG. 1 is a top view showing the layout of conventional metal interconnects. As the level of integration for semiconductor devices continues to increase, the aspect ratio of contact openings must be reduced to avoid difficulties encountered while carrying out etching and material deposition. At present, the contact plug 20 in FIG. 1 has a critical dimension greater than the metal line 10 so that more metal lines 10 can be packed within the limited surface area of a chip.
With the contact plug 20 having a larger critical dimension, the alignment tolerance in the process of forming the contact opening is greatly reduced. Should an alignment error occur, a neighboring conductive structure such as the conductive layer of a gate structure may be exposed leading to a possible short circuit between a subsequently formed contact plug and the conductive structure.
Furthermore, with the critical dimension of the contact plug 20 greater than the metal line 10 and the pitch between neighboring metal line 10 reduced, the overlay tolerance in photolithographic processing of the metal lines 10 is relatively small. Any minor misalignment will likely lead to an unwanted electrical connection or short-circuit between a metal line 10 and a neighboring plug.